How it works in 'timescale…if i write 1ns/100ps
timescale is a compiler directive (note the back-tick). Like other compiler directives (like the macro definitions) its scope is global. But since the directive may be specified multiple times, the later invocation overwrites all previous ones in the ensuing code.
With this directive, you specify timeunit and timeprecision to be used in the simulation. At a result, wherever in your code you put a delay without specifying the timeunit, the value specified by timescale is used.
Because of the macro-like global nature of timescale directive, its application is subject to the order in which verilog code files are read by the compiler (by way of include directives). Changing the order of include directives may change how the different timescale directives may apply to your code. Therefor specifying timescale directive requires a project wide discipline. Some projects make it mandatory to specify it on top of every file. In some other projects, you may be asked to use a global value and avoid putting this directive in the code files altogether.
Note that most verilog compilers allow you to specify timescale parameters via command line arguments as well.