Simulator about EUVM

Hi, our team is interested in E-UVM
we are using SNPS VCS
Can EUVM be compiled & simulated with SNPS VCS? If possible, could you tell me some tutorial about it?

Best Regards,

Thank you for your interest.

EUVM can certainly be compiled and simulated with VCS or any other Simulator that supports PLI. Unfortunately, we do not have access to VCS to be able to write a tutorial on EUVM integration with VCS. On the other hand, I can share with you the setup and makefiles required to run EUVM testbench with Modelsim or with Icarus Verilog. I believe it will not be difficult to port such a setup to work with VCS.

We are also in the process of making another release of EUVM that will support “unique”, “inside” and some other variations in constraint constructs.

Thanks for your response.

So, we decided to migrate our UVM testbench with VCS to EUVM testbench.
I installed euvm-1.0-beta9 with euvm-1.0-beta9-arm-linux-gnueabihf
To make simple EUVM testbench with VCS, downloaded EUVM testbench at
Is this EUVM testbench right?
If yes, please tell me how to modify setup and makefiles and how to compile and simulate test case to run as VCS.
Or if it is not an EUVM testbench, please tell me how to download EUVM testbench.

Thanks and Regards,