Objection mechanism in UVM

Why we need raise and drop objection in UVM? is it mandatory to use?

The idea behind an objection raise and drop is to synchronize all components before moving onto the next phase. If there are child components that has raised an objection for say, main_phase, simulation will wait until all objections have been dropped before moving to the next phase. When an objection is raised, UVM testbench structure keeps a count of how many objections it received and decrements the count as other components drop previously raised objections. If you raise an objection and do not drop it, the current phase will never end and simulation would most likely hang.

Components like drivers/sequencers have normally a run_phase() that will have a forever loop that runs as long as sequence items are received and hence does not need any further raise/drop objections

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