Need a help with building up EUVM testbench

Hi, I am trying to building up EUVM testbench, but I don’t know how to start.
Please, share the setup & makefiles for running EUVM testbench with modelsim or any simulators.

Thank you in advance!!

You may want to take a look at the following repository. A makefile that works with opensource Icarus Verilog simulator is included in the sim folder.