How Mem Declare and Access in euvm?

As in SV mem is declared as:
logic [3:0]addr;
logic [3:0] rdata,wdata;
bit [3:0] mem [0:16];
and access as
else begin
initial begin
So how can i do the same thing in euvm?

What is your purpose of creating a memory model? I am asking, since you an unusual code that does not have a clock, but yet you have RTL like signals which are not required for a verification model.

If you want to model is a memory for the purpose of a scoreboard, it would just be an array. If you need a temporal model of a memory, it is possible in EUVM, but is usually not needed.

I want to implement tempeoral memory in scoreboard. How can I implement this in euvm?

You do not do that. UVM uses TLM methodology. The temporal part of the testbench is generally limited to the Bus Functional Models in the driver and the monitors.

At scoreboard level, if you want to have some information about time, it will be in form of data. Time will be stored as data (as one of the fields in a transaction).