Compilation issue in euvm testbench

Currently, we are working on the euvm porting of SV testbench. Previously whole environment design files(.v, .sv, .vhdl) & test-bench files(.sv, .c, .h) are compiled and simulated with Model sim.
After porting the SV testbench into euvm testbench files (.d, .v) files are getting compiled with iverilog and ldc2 compilers.
But when we have to integrate both design and euvm environment which simulators we should use?
Actually I have tried to compile the design files with iverilog but it is showing errors when it encounters SV constructs.
Please help us regarding this.